Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
2008 (English)In: European Microwave Week 2008, Conference Proceedings, 27-31 October 2008, Amsterdam, The Netherlands, IEEE , 2008, 1207-1210 p.Conference paper (Refereed)
This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.
Place, publisher, year, edition, pages
IEEE , 2008. 1207-1210 p.
CMOS integrated circuits, impedance matching, power amplifiers, transformers, transistors, wireless LAN
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-21009DOI: 10.1109/EUMC.2008.4751677ISBN: 978-2-87487-006-4OAI: oai:DiVA.org:liu-21009DiVA: diva2:240380
The 38th IEEE European Microwave Conference (EuMC), October 28-30, Amsterdam, The Netherlands