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Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2009 (English)In: Proceedings of 9th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Diego, CA, USA, January 19–21, IEEE , 2009, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design of two low- voltage differential class-E power amplifiers (PA) for DECT and Bluetooth fabricated in 130 nm CMOS. In order to minimize the on-chip losses and to achieve a high efficiency at low supply voltages, the PAs do not use on-chip output matching networks. At 1.5V supply voltage, the DECT PA delivers +26.4 dBm of output power with a drain efficiency (DE) and power-added efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA delivers +22.7 dBm at IV with a DE and PAE of 48% and 36%, respectively. A continuous long-term test of 100 hours proves the reliability of the design.

Place, publisher, year, edition, pages
IEEE , 2009. 1-4 p.
Keyword [en]
Bluetooth, CMOS integrated circuits, cordless telephone systems, differential amplifiers, power amplifiers, reliability
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-21022DOI: 10.1109/SMIC.2009.4770499ISBN: 978-1-4244-3940-9 (print)OAI: oai:DiVA.org:liu-21022DiVA: diva2:240417
Conference
IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09, 19-21 January, San Diego, CA, USA
Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2011-11-08Bibliographically approved
In thesis
1. Power Amplifier Circuits in CMOS Technologies
Open this publication in new window or tab >>Power Amplifier Circuits in CMOS Technologies
2009 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The wireless market has experienced a remarkable development and growth since the introduction of the first mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, a prime goal of the IC manufacturers is to provide low-cost solutions.

The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming significantly harder to meet the stringent requirements on linearity, output power, and power efficiency of PAs at lower supply voltages. This has recently triggered extensive studies to investigate the impact of different circuit techniques, design methodologies, and design trade-offs on functionality of PAs in nanometer CMOS technologies.

This thesis addresses the potential of integrating linear and highly efficient PAs and PA architectures in nanometer CMOS technologies at GHz frequencies. In total four PAs have been designed, two linear PAs and two switched PAs. Two PAs have been designed in a 65nm CMOS technology, targeting the 802.11n WLAN standard operating in the 2.4-2.5GHz frequency band with stringent requirements on linearity. The first linear PA is a two-stage amplifier with LC-based input and interstage matching networks, and the second linear PA is a two-stage PA with transformer-based input and interstage matching networks. Both designs were evaluated for a 72.2Mbit/s, 64-QAM 802.11n OFDM signal with a PAPR of 9.1dB. Both PAs fulfilled the toughest EVM requirement of the standard at average output power levels of 9.4dBm and 11.6dBm, respectively. Matching techniques in both PAs are discussed as well.

Two Class-E PAs have been designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The first PA is intended for DECT, while the second is intended for Bluetooth. At 1.5V supply voltage and 1.85GHz, the DECT PA delivered +26.4dBm of output power with a drain efficiency (DE) and poweradded efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA had an output power of +22.7dBm at 1.0V with a DE and PAE of 48% and 36%, respectively, at 2.45GHz. The Class-E amplifier stage is also suitable for employment in different linearization techniques like Polar Modulation and Outphasing, where a highly efficient Class-E PA is crucial for a successful implementation.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. 83 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1414
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-21030 (URN)LiU-TEK-LIC-2009:22 (Local ID)978-91-7393-530-2 (ISBN)LiU-TEK-LIC-2009:22 (Archive number)LiU-TEK-LIC-2009:22 (OAI)
Presentation
2009-11-04, Glashuset, Campus Valla, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Supervisors
Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2010-04-05Bibliographically approved
2. CMOS RF Power Amplifiers for Wireless Communications
Open this publication in new window or tab >>CMOS RF Power Amplifiers for Wireless Communications
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions.

The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies.

This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals.

The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology.

The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated.

The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals.

The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion.

The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2011. 94 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1399
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71852 (URN)978-91-7393-059-8 (ISBN)
Public defence
2011-11-25, KEY1, Key-huset, Campus Valla, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Supervisors
Available from: 2011-11-08 Created: 2011-11-07 Last updated: 2011-11-16Bibliographically approved

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Fritzin, JonasAlvandpour, Atila

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