Geometry optimization in basic CMOS cells for improved power, leakage, and noise performances
2008 (English)In: Proc. Int. Conf. Advances in Electronics and Micro-electronics, ENICS'08, IEEE , 2008, 48-53 p.Conference paper (Refereed)
The rising demand for portable system is increasing the importance of low power as a design consideration. In this sense, leakage power is increasing much faster than dynamic power at smaller dimensions. Peak values of supply current are related to noise injected into the substrate and/or propagated through supply network, limiting the performances of the sensitive analog and RF portions of mixed-signal circuits. This paper analyses how these three aspects, dynamic power, leakage power and peak power, can be considered together, optimizing the sizing and design of basic cells, with a reduced degradation in performances. The suited sizing of basic cells, show the benefits of the proposed technique, validated through simulation results on 130 nm nand, nor and inverter cells.
Place, publisher, year, edition, pages
IEEE , 2008. 48-53 p.
CMOS integrated circuits, circuit optimization, circuit simulation, geometry, low-power electronics, mixed analog-digital integrated circuits, power supply circuits
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-21832DOI: 10.1109/ENICS.2008.26ISBN: 978-0-7695-3370-4OAI: oai:DiVA.org:liu-21832DiVA: diva2:241804
2008 International Conference on Advances in Electronics and Micro-electronics