A static CMOS master-slave flip-flop experiment
2000 (English)In: Proc. 7th IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'00, IEEE , 2000, 870-873 vol.2 p.Conference paper (Refereed)
A variant of a classical master-slave flip-flop based on transmission gates is derived where the transmission gates are replaced by static CMOS gates. The transmission gate flip-flop and the variant are evaluated along with one flip-flop based on C2MOS latches and another based on SR latches. All flip-flops are edge-triggered. The propagation delay, set-up time, and hold time are estimated using a 0.35 μm process. The author also investigates how the power dissipation at the maximal clock frequency varies when the supply voltage is scaled, both when the device geometry is kept constant and when it is scaled to yield good noise margins. In comparison, the variant on master-slave flip-flop has short propagation delay, but is only average in terms of throughput and power consumption. The flip-flop realized with C2 MOS latches seems to be a better candidate for a general-purpose implementation when voltage scaling is an option
Place, publisher, year, edition, pages
IEEE , 2000. 870-873 vol.2 p.
CMOS logic circuits, delay estimation, flip-flops, integrated circuit noise
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-21853DOI: 10.1109/ICECS.2000.913014ISBN: 0-7803-6542-9OAI: oai:DiVA.org:liu-21853DiVA: diva2:241831
The 7th IEEE International Conference on Electronics, Circuits and Systems, 2000, Jounieh, Lebanon.