Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study
2004 (English)In: IEEE International SOC Conference, 2004. Proceedings., Piscataway: IEEE, Inc. , 2004, 147-148 p.Conference paper (Refereed)
A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.
Place, publisher, year, edition, pages
Piscataway: IEEE, Inc. , 2004. 147-148 p.
integrated circuit, communication, bus, equalizer
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-22540DOI: 10.1109/SOCC.2004.1362384Local ID: 1801ISBN: 0-7803-8445-8OAI: oai:DiVA.org:liu-22540DiVA: diva2:242853
IEEE International SOC Conference, 2004 (SOCC). Santa Clara California, September 12-15 2004.