liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2004 (English)In: IEEE International SOC Conference, 2004. Proceedings., Piscataway: IEEE, Inc. , 2004, 147-148 p.Conference paper, Published paper (Refereed)
Abstract [en]

A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.

Place, publisher, year, edition, pages
Piscataway: IEEE, Inc. , 2004. 147-148 p.
Keyword [en]
integrated circuit, communication, bus, equalizer
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-22540DOI: 10.1109/SOCC.2004.1362384Local ID: 1801ISBN: 0-7803-8445-8 (print)OAI: oai:DiVA.org:liu-22540DiVA: diva2:242853
Conference
IEEE International SOC Conference, 2004 (SOCC). Santa Clara California, September 12-15 2004.
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-12-17
In thesis
1. Equalization techniques for multi-Gb/s multi-drop buses
Open this publication in new window or tab >>Equalization techniques for multi-Gb/s multi-drop buses
2007 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The development of electronics is continuously expanding the possibilities of computational power and system complexity. The progress has in the past and in the foreseeable future primarily been achieved by the development of integrated circuit technologies. Though the trend is to integrate more and more functionality on a single chip (usually referred to as the system-on-chip concept). technology. manufacturing. system integration. and enterprise business model considerations prevent the system-on-chip concept to prevail in all electronic systems. Therefore. the continuous progresses in integrated circuit data handling capabilities impose faster inter chip communication.

Though the improvements in materials and devices have to some extent fulfilled these increased communication speed requirements, the pace has been slower than the development of the integrated circuits. For many applications, this has made the communication channels between integrated circuits a limiting factor.

To tackle these problems, electronic systems tend to utilize more point to point high-speed high quality links for chip-to-chip communication. This approach only partially solves the problem and it can for various reasons not be used for a ll systems. One type of system where high-speed narrow links have been used. but where the dominating bus structure s till is a wide multi-drop structure. is the memory interface of a standard computer. Improvements in the electrical properties of this type of bus have so far been enough to keep up with the increased demands for higher data rates, but it will not be able to do so in the future. This thesis presents work exploiting the possibilities of using equalizing techniques to drastically improve the data handling speed of multi-drop memory buses. The approach has been to accept the speed limiting mechanisms of the multi-drop bus and to exploit the fast deve lopment of integrated circuit's on-chip computational power to enable higher data rates.

The thesis analyses the speed limiting factors on a chip-to-chip multi-drop channel. Different equalization techniques (including blind adaptive techniques) are presented and compared from a multi-drop bus point of view. A new equalizer implementation structure is presented and results from test chip measureme nts are included. Different computational abilities for the memory chip and the memory host chip make us suggest the use of asymmetric equalization relying on the reciprocal properties of the channel. Finally. issues related to evaluation of high -speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2007. 60 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1298
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-37702 (URN)37748 (Local ID)978-91-85715-80-0 (ISBN)37748 (Archive number)37748 (OAI)
Presentation
2007-02-20, Glashuset, Linköpings universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2016-12-08

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Fredriksson, HenrikSvensson, Christer

Search in DiVA

By author/editor
Fredriksson, HenrikSvensson, Christer
By organisation
Electronic DevicesThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 97 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf