An RF sampling downconversion filter for a receiver front-end
2004 (English)In: The 2004 47th Midwest Symposium on Circuits and Systems, 2004: MWSCAS '04, Piscataway: IEEE, Inc. , 2004, 165-168 p.Conference paper (Refereed)
An integrable front-end architecture for WLAN applications in the 2.4 GHz band is described in this paper. It is based on a multi-functional switched-capacitor block, which performs RF sampling, quadrature downconversion to IF, tunable IF filtering, downconversion to baseband, and sampling rate decimation. The proposed RF sampling downconversion filter is designed in a 0.18-μm CMOS technology. In the downconverted channel band the anti-alias suppression is more than 26 dB. The signal gain is 8 dB, the noise figure is 22 dB, and the IIP3 is at +11 dBm. The image rejection is better than 66 dB. Without the clock generation block the sampling mixer and downconversion filter consume 2.9 mW power.
Place, publisher, year, edition, pages
Piscataway: IEEE, Inc. , 2004. 165-168 p.
Analog integrated circuits, mixers, radio receivers, sample-and-hold circuits, switched-capacitor filters
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-22542DOI: 10.1109/MWSCAS.2004.1353923Local ID: 1805ISBN: 0-7803-8346-XOAI: oai:DiVA.org:liu-22542DiVA: diva2:242855
The 47th IEEE International Midwest Symposium on Circuits and System, Hiroshima, Japan, July 25-28, 2004