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Topics on CMOS Image Sensors
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2005 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Today there exist several applications where a real visible scene needs to be sampled to electrical signals, e.g., video cameras, digital still cameras, and machine vision systems. Since the 1970's charge-coupled device (CCD) sensors have primarily been used for this task, but during the last decade CMOS image sensors have become more and more popular. The demand for image sensors has lately grown very rapidly due to the increased market for, e.g., digital still cameras and the integration of image sensors in mobile phones.

The first out of three included papers presents a programmable multiresolution machine vision sensor with on-chip image processing capabilities. The sensor comprises an innovative multiresolution sensing area, 1536 ND converters, and a SIMD array of 1536 bit-serial processors with corresponding memory. The SIMD processor array can deliver more than 100 GOPS sustained and the onchip pixel-analyzing rate can be as high as 4 Gpixels/s. The sensor is intended for high-speed multisense imaging where, e.g., color, greyscale, internal material light scatter, and 3-D profiles are captured simultaneously. Experimental results showing very good image characteristics and a good digital to analog noise isolation are presented.

The second paper presents a mathematical analysis of how temporal noise is transformed by quantization. A new method for measuring temporal noise with a low-resolution ADC and then accurately refer it back to the input of the ADC is shown. The method is, for instance, applicable to CMOS image sensors where photon shot noise is commonly used for determining conversion gain and quantum efficiency. Experimental tests have been carried out using the above mentioned sensor, which has an on-chip ADC featuring programmable gain and offset. The measurements verify the analysis and the method.

The third paper presents a new column parallel ADC architecture, named simultaneous multislope, suitable for array implementations in, e.g., CMOS image sensors. The simplest implementation of the suggested architecture is almost twice as fast as a conventional slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed using the above mentioned sensor, which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2005. , 75 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1182
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-22627Local ID: 1907ISBN: 91-85299-91-x OAI: oai:DiVA.org:liu-22627DiVA: diva2:242940
Public defence
2005-08-26, Glashuset, Linköpings universitet, Linköping, 13:15 (Swedish)
Opponent
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-10-31
List of papers
1. A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging
Open this publication in new window or tab >>A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging
2005 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 6, 1350-1359 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a multiresolution general-purpose high-speed machine vision sensor with on-chip image processing capabilities. The sensor comprises an innovative multiresolution sensing area, 1536 A/D converters, and a SIMD array of 1536 bit-serial processors with corresponding memory. The sensing area consists of an area part with 1536 × 512 pixels, and a line-scan part with a set of rows with 3072 pixels each. The SIMD processor array can deliver more than 100 GOPS sustained and the on-chip pixel-analysing rate can be as high as 4Gpixels/s. The sensor is ideal for high-speed multisense imaging where, e.g., color, greyscale, internal material light scatter, and 3-D profiles are captured simultaneously. When running only 3-D laser triangulation, a data rate of more than 20 000 profiles/s can be achieved when delivering 1536 range values per profile with 8 bits of range resolution. Experimental results showing very good image characteristics and a good digital to analog noise isolation are presented.

Keyword
APS, CMOS image sensors, laser triangulation, machine vision, MAPP, multiresolution, multisense, smart vision sensors, 3-D
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22624 (URN)10.1109/JSSC.2005.848029 (DOI)000229447900015 ()1904 (Local ID)1904 (Archive number)1904 (OAI)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2017-12-13
2. Elimination of quantization effects in measured temporal noise
Open this publication in new window or tab >>Elimination of quantization effects in measured temporal noise
2004 (English)In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Piscataway: IEEE Corp. , 2004, 932-935 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a mathematical analysis of how temporal noise is transformed by quantization. A new method for measuring temporal noise with a low-resolution ADC and then accurately refer it back to the input of the ADC is shown. The method is, for instance, applicable to CMOS image sensors where photon shot noise is commonly used for determining conversion gain and quantum efficiency. Experimental tests have been carried out using a custom designed CMOS image sensor with an on-chip ADC featuring programmable gain and offset. The measurements verify the analysis and the method, e.g. noise levels of 0.11 LSB was measured with an accuracy 30 times higher than a traditional method would give.

Place, publisher, year, edition, pages
Piscataway: IEEE Corp., 2004
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22821 (URN)10.1109/ISCAS.2004.1329158 (DOI)2159 (Local ID)0-7803-8251-X (ISBN)2159 (Archive number)2159 (OAI)
Note

Received the Sensory Systems track Best Paper Award.

Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-10-31
3. A new simultaneous multislope ADC architecture for array implementations
Open this publication in new window or tab >>A new simultaneous multislope ADC architecture for array implementations
2006 (English)In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, E-ISSN 1558-125X, Vol. 53, no 9, 921-925 p.Article in journal (Refereed) Published
Abstract [en]

This brief presents a new simultaneous multislope analog-digital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-35616 (URN)10.1109/TCSII.2006.881817 (DOI)27966 (Local ID)27966 (Archive number)27966 (OAI)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2017-12-13

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