The fast development of wireless communication systems asks for more flexible and more cost-effective radio architectures. A long term goal is a software defined radio, where communication standards are chosen by reconfiguration of hardware. Direct analog-to-digital conversion of the radio frequency (RF) signal is considered unrealistic due to too high requirements on the analog-to-digital converter. This motivates a need for a highly flexible analog front-end that can be fully integrated in a low cost complementary metal-oxide-semiconductor (CMOS) technology.
This thesis exploits the possibility to utilize switched-capacitor (SC) technique for front-end sampling, downconversion, filtering, and decimation. As a result, a new integrable radio receiver front-end architecture is proposed, based on an RF sampling downconversion (RFSD) filter as a discrete-time multi-functional block in SC technique. The front-end architecture is intended for wireless local area network (WLAN) applications in the 2.4 GHz frequency band. A test chip of the RFSD filter has been fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable bandpass filtering, downconversion to baseband, and decimation of the sampling rate. The RFSD filter full functionality has been achieved for input sampling rates up to 1 072 MS/s. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels and possibly different bands.
A MOS switch linearization method for a track-and-hold (T/H) circuit is also described in the thesis. This method has been verified with a test chip in a 0.35-μm CMOS technology. The test chip measurement results demonstrate about 5 dB lower harmonic distortion in comparison to an ordinary T/H circuit. Based on the proposed linearization method, a down-conversion sampling mixer has been designed in a 0.35-μm CMOS process. lt has an input-referred third-order intercept point of +22 dBm for a 1.6 GHz input signal, measured at a sampling rate of 1.55 GS/s. The downconversion sampling mixer noise properties are investigated by a noise analysis. The noise analysis is validated by measurement results, which show that the jitter-induced noise is critical for low sampling rates. The downconversion sampling mixer is also proved to be applicable for WCDMA and DECT wireless communication standards in a wideband low intermediate frequency receiver architecture.
To sum up, the presented CMOS sampling receiver front-end is suitable to realize a flexible and highly integrable low cost radio architecture.
Linköping: Linköpings universitet , 2004. , 62 p.
2004-07-01, Sal Visionen, Linköping Universitet, Linköping, 13:15 (Swedish)