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Direct RF sampling receivers for wireless systems in CMOS technology
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2004 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The fast development of wireless communication systems asks for more flexible and more cost-effective radio architectures. A long term goal is a software defined radio, where communication standards are chosen by reconfiguration of hardware. Direct analog-to-digital conversion of the radio frequency (RF) signal is considered unrealistic due to too high requirements on the analog-to-digital converter. This motivates a need for a highly flexible analog front-end that can be fully integrated in a low cost complementary metal-oxide-semiconductor (CMOS) technology.

This thesis exploits the possibility to utilize switched-capacitor (SC) technique for front-end sampling, downconversion, filtering, and decimation. As a result, a new integrable radio receiver front-end architecture is proposed, based on an RF sampling downconversion (RFSD) filter as a discrete-time multi-functional block in SC technique. The front-end architecture is intended for wireless local area network (WLAN) applications in the 2.4 GHz frequency band. A test chip of the RFSD filter has been fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable bandpass filtering, downconversion to baseband, and decimation of the sampling rate. The RFSD filter full functionality has been achieved for input sampling rates up to 1 072 MS/s. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels and possibly different bands.

A MOS switch linearization method for a track-and-hold (T/H) circuit is also described in the thesis. This method has been verified with a test chip in a 0.35-μm CMOS technology. The test chip measurement results demonstrate about 5 dB lower harmonic distortion in comparison to an ordinary T/H circuit. Based on the proposed linearization method, a down-conversion sampling mixer has been designed in a 0.35-μm CMOS process. lt has an input-referred third-order intercept point of +22 dBm for a 1.6 GHz input signal, measured at a sampling rate of 1.55 GS/s. The downconversion sampling mixer noise properties are investigated by a noise analysis. The noise analysis is validated by measurement results, which show that the jitter-induced noise is critical for low sampling rates. The downconversion sampling mixer is also proved to be applicable for WCDMA and DECT wireless communication standards in a wideband low intermediate frequency receiver architecture.

To sum up, the presented CMOS sampling receiver front-end is suitable to realize a flexible and highly integrable low cost radio architecture.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2004. , 62 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 881
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-22634Local ID: 1917ISBN: 9173739650 (print)OAI: oai:DiVA.org:liu-22634DiVA: diva2:242947
Public defence
2004-07-01, Sal Visionen, Linköping Universitet, Linköping, 13:15 (Swedish)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2017-12-15
List of papers
1. A 1 GHz linearized CMOS track-and-hold circuit
Open this publication in new window or tab >>A 1 GHz linearized CMOS track-and-hold circuit
2002 (English)In: IEEE International Symposium on Circuits and Systems, 2002: ISCAS 2002, 2002, 577-580 p.Conference paper, Published paper (Refereed)
Abstract [en]

A simple solution for linearization of the MOS sampling switch is proposed. It improves the SFDR of a T/H circuit and is suitable for high-speed applications. Sampling at a constant gate-source voltage minimizes sampling errors due to variable MOS sampling switch ON-conductance and channel charge injection, and also eliminates input-dependent sampling instant variation. The proposed linearized T/H circuit is fabricated in a 0.35-μm CMOS process. Test measurements show the sampling of a 1 GHz signal.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34846 (URN)23650 (Local ID)0-7803-7448-7 (ISBN)23650 (Archive number)23650 (OAI)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, 26-29 May 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-18
2. An RF sampling front-end for a digital receiver
Open this publication in new window or tab >>An RF sampling front-end for a digital receiver
2002 (English)In: Proceedings of the 20th IEEE NORCHIP Conference, Copenhagen: TechnoData A/S , 2002, 21-26 p.Conference paper, Published paper (Refereed)
Abstract [en]

An RF sampling front-end is presented in this paper. The front-end specifications are defined using the GSM-1800 requirements. The implementation of the front-end has been concentrated on a sampler, which is expected to be the most critical block. A linearized sampler is proposed to achieve the high linearity specifications. The sampler enables sampling of a wide band signal at high frequencies. lt is designed in 0.35-μm CMOS process. The simulation results proves, that the sampler achieves high linearity up to carrier frequency. To clock the linearized sampler a low-jitter clock path is presented. lt reduces the clock path sensitivity to power supply variations and protects the clock from additional on-chip jitter.

Place, publisher, year, edition, pages
Copenhagen: TechnoData A/S, 2002
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34847 (URN)23651 (Local ID)23651 (Archive number)23651 (OAI)
Conference
20th IEEE NORCHIP Conference, Copenhagen, Denmark, November 11-12, 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-18
3. A 1.6 GHz downconversion sampling mixer in CMOS
Open this publication in new window or tab >>A 1.6 GHz downconversion sampling mixer in CMOS
2003 (English)In: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003: ISCAS '03, Piscataway: IEEE , 2003, 725-728 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a downconversion sampling mixer design in CMOS. A MOS switch linearization technique is utilized, which enables high frequency sampling of an RF signal. The measurement results show a 1.6 GHz input signal downconversion with a sampling rate of 1.55 GHz, +22 dBm IIP3, 1.4 ps sampling jitter, 8 dB conversion loss and 25 dB noise figure. The chip is fabricated in a 0.35 μm 3.3 V CMOS process and bonded directly onto a printed circuit board. The downconversion sampling mixer occupies an active area of 0.05 mm2 and consumes 43 mW power.

Place, publisher, year, edition, pages
Piscataway: IEEE, 2003
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34769 (URN)10.1109/ISCAS.2003.1205666 (DOI)23191 (Local ID)0-7803-7761-3 (ISBN)23191 (Archive number)23191 (OAI)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS, Bangkok, Thailand, 25-28 May 2003
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-01-08
4. Noise analysis of downcenversion sampling mixer
Open this publication in new window or tab >>Noise analysis of downcenversion sampling mixer
2003 (English)In: Proceedings of the European Conference on Circuit Theory and Design (ECCTD), 2003, 181-184 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we address noise properties of an RF downconversion sampling mixer. The relevant noise mechanisms in a SIH circuit are reviewed and investigated. The jitter-induced noise that originates from the sampling clock and the switch driver is shown to be critical in the RF front-end application. Some practical design ideas aimed at optimization of the circuit parameters and the sampling frequency are included. The noise analysis is verified experimentally with a CMOS test chip intended for RF signals up to 2 GHz. The circuit structure and the relevant measurement setup are presented. The obtained results validate our noise analysis.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34776 (URN)23198 (Local ID)23198 (Archive number)23198 (OAI)
Conference
ECCTD '03, The 16th European Conference on Circuit Theory and Design, 1 - 4 September 2003, Kraków, Poland
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-01-08
5. Downconversion sampling mixer for wideband low-IF receiver
Open this publication in new window or tab >>Downconversion sampling mixer for wideband low-IF receiver
2003 (English)In: Proceedings of the 10th International Conference on Mixed Design of Integrated Curcuits and Systems (MIXDES), Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz , 2003, 208-213 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we discuss applicability of a sampling mixer in a wideband low-IF receiver architecture. It is aimed at a highly digitized structure where the wideband AD conversion is performed at low-IF, and the channel selection and demodulation are left for DSP. While aliasing in downconversion is avoided with a proper choice of the subsampling rate, to cope with the close image problem the IQ scheme must be used as well. An extra constraint is imposed on the subsampling frequency in this way. Noise and linearity properties of the sampling mixer are discussed in a context of the front-end performance, and next, with respect to selected RF standard specifications. The discussion is based on the experience gained with a sampling mixer chip designed and manufactured in CMOS 0.35 µm process. The analysis performed qualifies sampling mixers to be of use in standard RF applications especially when low nonlinear distortions and wide dynamic range are required.

Place, publisher, year, edition, pages
Lodz, Poland: Dpt of Microelectronics and Computer Science, Technical University of Lodz, 2003
Keyword
Downconversion Mixer, Subsampling, Wideband Low-IF Receiver, RF-CMOS design
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34777 (URN)23199 (Local ID)23199 (Archive number)23199 (OAI)
Conference
10th International Conference Mixed Design of Integrated Circuits and Systems Łódź, Poland, 26-28 June 2003
Note

Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-01-08
6. An RF sampling downconversion filter for a receiver front-end
Open this publication in new window or tab >>An RF sampling downconversion filter for a receiver front-end
Show others...
2004 (English)In: The 2004 47th Midwest Symposium on Circuits and Systems, 2004: MWSCAS '04, Piscataway: IEEE, Inc. , 2004, 165-168 p.Conference paper, Published paper (Refereed)
Abstract [en]

An integrable front-end architecture for WLAN applications in the 2.4 GHz band is described in this paper. It is based on a multi-functional switched-capacitor block, which performs RF sampling, quadrature downconversion to IF, tunable IF filtering, downconversion to baseband, and sampling rate decimation. The proposed RF sampling downconversion filter is designed in a 0.18-μm CMOS technology. In the downconverted channel band the anti-alias suppression is more than 26 dB. The signal gain is 8 dB, the noise figure is 22 dB, and the IIP3 is at +11 dBm. The image rejection is better than 66 dB. Without the clock generation block the sampling mixer and downconversion filter consume 2.9 mW power.

Place, publisher, year, edition, pages
Piscataway: IEEE, Inc., 2004
Keyword
Analog integrated circuits, mixers, radio receivers, sample-and-hold circuits, switched-capacitor filters
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22542 (URN)10.1109/MWSCAS.2004.1353923 (DOI)1805 (Local ID)0-7803-8346-X (ISBN)1805 (Archive number)1805 (OAI)
Conference
The 47th IEEE International Midwest Symposium on Circuits and System, Hiroshima, Japan, July 25-28, 2004
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-08
7. A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS
Open this publication in new window or tab >>A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS
Show others...
2005 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 6, 1265-1277 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-μm CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP3 of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm2.

Keyword
Bandpass filters, CMOS analog integrated circuits, Mixers, Radio receivers, Sample and hold circuits, Switched-capacitor filters
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-45438 (URN)10.1109/JSSC.2005.848027 (DOI)
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-13

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  • Other locale
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  • text
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