Optical communication develops very fast and is today the main method for long distance wired communication. However cost is still high. Looking back to the evolution of optical transmission systems, one main objective of system development has become more and more important; minimize cost per gigabytes per second per kilometre, Gb/s/km. One possible solution is to utilize cost effective CMOS technology for all electronic parts and replace optical dispersion compensation with electronic equalization. Recent research indicates that deep submicron CMOS technology indeed can be used for realizing highly integrated optical receivers at data rates of tens of gigabit per second. Recent research also shows that expensive optical dispersion compensators can be replaced with electrical equalizers.
This thesis describes an optical receiver in CMOS. The optical receiver consists of a differential transimpedance amplifier, a differential and four times interleaved decision feedback equalizer, DFE coefficient update unit and symbol synchronization. The objective of the thesis is to find a scalable optical receiver topology for high speed, wide input range, low power supply sensitivity and reasonable input related noise, for a CMOS technology with a relative low fT The target is to reach 2.5 Gb/s in a 3.3 V 0.35μm CMOS process. Due to the risk for instability for cascaded broadband amplifiers, the amplifier stability related to the power supply impedance is also investigated
Measurements on the differential transimpedance amplifier show 72 dBΩ transimpedance gain and 1.4 GHz bandwidth. Eye diagrams at data rate of 2.5 Gb/s show a dynamic range of more than 60 dB. The performance is reached with a three-stage transimpedance amplifier, utilizing differential high-speed stages and carefully chosen peaking frequencies.
By measurements on the equalizer, a 2 Gb/s NRZ pattern are sent through a 5 m coaxial cable with an 8 cm open stub for echo generation. The coaxial cable with the stub introduces such large intersymbol interference that there is no eye opening left. The equalizer recovers then the sent data correctly.
The equalizer is clocked with a DLL, which is separately tested. The DLL has a new type of delay cell with low power supply sensitivity. The delay range is 0.31 ns to 21.8 ns. For 0.5 ns delay of a 500 MHz signal, the delay increases 2.5 % if the power supply is decreased from 3.3 V to 3 V.
The DFE coefficient update unit and the symbol synchronization is implemented in verilog-A and verified with simulations.
Linköping: Linköpings universitet , 2004. , 94 p.
2004-11-12, Sal Visionen, Linköpings universitet, Linköping, 10:15 (Swedish)