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High speed CMOS optical receiver
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2004 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Optical communication develops very fast and is today the main method for long distance wired communication. However cost is still high. Looking back to the evolution of optical transmission systems, one main objective of system development has become more and more important; minimize cost per gigabytes per second per kilometre, Gb/s/km. One possible solution is to utilize cost effective CMOS technology for all electronic parts and replace optical dispersion compensation with electronic equalization. Recent research indicates that deep submicron CMOS technology indeed can be used for realizing highly integrated optical receivers at data rates of tens of gigabit per second. Recent research also shows that expensive optical dispersion compensators can be replaced with electrical equalizers.

This thesis describes an optical receiver in CMOS. The optical receiver consists of a differential transimpedance amplifier, a differential and four times interleaved decision feedback equalizer, DFE coefficient update unit and symbol synchronization. The objective of the thesis is to find a scalable optical receiver topology for high speed, wide input range, low power supply sensitivity and reasonable input related noise, for a CMOS technology with a relative low fT The target is to reach 2.5 Gb/s in a 3.3 V 0.35μm CMOS process. Due to the risk for instability for cascaded broadband amplifiers, the amplifier stability related to the power supply impedance is also investigated

Measurements on the differential transimpedance amplifier show 72 dBΩ transimpedance gain and 1.4 GHz bandwidth. Eye diagrams at data rate of 2.5 Gb/s show a dynamic range of more than 60 dB. The performance is reached with a three-stage transimpedance amplifier, utilizing differential high-speed stages and carefully chosen peaking frequencies.

By measurements on the equalizer, a 2 Gb/s NRZ pattern are sent through a 5 m coaxial cable with an 8 cm open stub for echo generation. The coaxial cable with the stub introduces such large intersymbol interference that there is no eye opening left. The equalizer recovers then the sent data correctly.

The equalizer is clocked with a DLL, which is separately tested. The DLL has a new type of delay cell with low power supply sensitivity. The delay range is 0.31 ns to 21.8 ns. For 0.5 ns delay of a 500 MHz signal, the delay increases 2.5 % if the power supply is decreased from 3.3 V to 3 V.

The DFE coefficient update unit and the symbol synchronization is implemented in verilog-A and verified with simulations.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2004. , 94 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 904
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-22637Local ID: 1921ISBN: 91-85295-61-2 (print)OAI: oai:DiVA.org:liu-22637DiVA: diva2:242950
Public defence
2004-11-12, Sal Visionen, Linköpings universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-25
List of papers
1. 3V CMOS 0.35 u transimpedance receiver for optical applications
Open this publication in new window or tab >>3V CMOS 0.35 u transimpedance receiver for optical applications
2001 (English)In: The 2001 IEEE International Symposium on Circuits and Systems, 2001: ISCAS 2001, Piscataway: IEEE , 2001, Vol. 4, 69-71 p.Conference paper, Published paper (Refereed)
Abstract [en]

A new class of receivers for optical applications is described. The novelty of the design is the high speed stage. The receiver is designed for low noise, high bandwidth and high transimpedance-bandwidth product. The receiver is driving a 50 Ω load. Post simulations on chip with all capacitance parasitics and a 0.5 pF diode capacitance, gives a 1.3 GHz bandwidth. For an input diode current of 1 uA=zero and 10 uA=one, the output signal is 0.15 V peak to peak and the output SNR is 23 dB

Place, publisher, year, edition, pages
Piscataway: IEEE, 2001
Keyword
Bandwidth, Capacitance, Inverters, Optical amplifiers, Optical buffering, Optical receivers, Radiofrequency amplifiers, Transconductance, Transfer functions, Voltage
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34959 (URN)10.1109/ISCAS.2001.922171 (DOI)24306 (Local ID)0-7803-6685-9 (ISBN)24306 (Archive number)24306 (OAI)
Conference
The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001. 6-9 May 2001 Sydney, NSW, Australia
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2015-04-09
2. Amplifier stability related to power supply impedance
Open this publication in new window or tab >>Amplifier stability related to power supply impedance
2004 (English)In: MIXDES 2004: proceedings of the 11th International Conference Mixed Design of Integrated Circuits and Systems / [ed] Andrzej Napieralski, Lodz, Poland: Technical University of Lodz , 2004, 151-156 p.Conference paper, Published paper (Refereed)
Abstract [en]

Amplifier stability related to power supply impedance is investigated. By comparing the impedance offered by the power supply rail with the power load impedance offered by the amplifier, a stability criterion is derived. We demonstrate the susceptibility to power supply impedance for different amplifiers and the choice of decoupling capacitance for stability

Place, publisher, year, edition, pages
Lodz, Poland: Technical University of Lodz, 2004
Keyword
Amplifier, Bondwire, Decoupling Capacitance, Flip Chip, Instability, Oscillation, Power Supply Impedance
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22483 (URN)1730 (Local ID)9788391928974 (ISBN)8391928977 (ISBN)1730 (Archive number)1730 (OAI)
Conference
The 11th International Conference Mixed Design of Integrated Circuits and Systems, Szczecin, Poland, 24-26 June 2004
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-25
3. 2.5 Gb/s, 72 dBΩ transimpedance amplifier in 0.35 μm CMOS
Open this publication in new window or tab >>2.5 Gb/s, 72 dBΩ transimpedance amplifier in 0.35 μm CMOS
2004 (English)Conference paper, Published paper (Other academic)
Abstract [en]

A differential transimpedance amplifier in a 3.3 V 0.35 μm CMOS process with an fT of 17 GHz is presented. Measurements demonstrate a transimpedance gain of 72 dBΩ and 1.4 GHz bandwidth. Eye diagrams at a data rate of 2.5 Gb/s show a dynamic range of more than 60 dB. The performance is reached with a three-stage transimpedance amplifier, utilizing differential high-speed stages and carefully chosen peaking frequencies.

Place, publisher, year, edition, pages
Macao: University of Macao, 2004
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22653 (URN)1940 (Local ID)1940 (Archive number)1940 (OAI)
Conference
The 2004 IEEJ 7th International Analog VLSI Workshop (AVLSIWS), 13th - 15th October, 2004, University of Macau, Macao SAR, China
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-25
4. Speed study of a 2,5 Gb/s equalizer for optical communication in a 3 V 0.35 μm CMOS process
Open this publication in new window or tab >>Speed study of a 2,5 Gb/s equalizer for optical communication in a 3 V 0.35 μm CMOS process
2002 (English)In: Proc. 2002 20th NORCHIP conference, Piscataway: IEEE , 2002Conference paper, Published paper (Refereed)
Abstract [en]

Decision feedback equalizers, DFE, can be used to increase the data rate of a fiber-optic communication system when intersymbol interference is a problem. The DFE must itself be fast to handle high bit rates. One way to manage high speed, is to introduce parallelism or interleaving. Requirements for the recovering time for the comparators and speed of memory cells will than decrease.

Place, publisher, year, edition, pages
Piscataway: IEEE, 2002
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-34839 (URN)23630 (Local ID)23630 (Archive number)23630 (OAI)
Conference
20th IEEE NORCHIP Conference, Copenhagen, Denmark, November 11-12, 2002
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-01-25
5. 2 Gb/s decision feedback equalizer in 3.3 V 0.35 µm CMOS
Open this publication in new window or tab >>2 Gb/s decision feedback equalizer in 3.3 V 0.35 µm CMOS
2004 (English)In: Circuits, Signals, and Systems (CSS 2004) / [ed] M.H. Rashid, 2004Conference paper, Published paper (Refereed)
Abstract [en]

A 2 Gb/s decision feedback equalizer is implemented in a 0.35 m CMOS process and experimentally demonstrated. Speed is enhanced through optimization of the unavoidable loop in a decision feedback equalizer, parallelism, differential current mode frontend, fast sense amplifier style comparators and single-phase flip-flops.

Keyword
comparator, current summation, decision feedback equalizer, feedback filter, parallelism, intersymbol interference, Schmitt trigger
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-87885 (URN)0-88986-453-5 (ISBN)
Conference
The IASTED International Conference on Circuits, Signals and Systems (CSS 2004), 28 Nov. - 1 Dec. 2004, Clearwater Beach, FL, USA
Available from: 2013-01-25 Created: 2013-01-25 Last updated: 2013-02-08
6. A scalable and robust rail-to-rail delay cell for DLLs
Open this publication in new window or tab >>A scalable and robust rail-to-rail delay cell for DLLs
2004 (English)In: IEEE International SOC Conference, 2004: Proceedings, Piscataway: IEEE, Inc. , 2004, 135-136 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a scalable and robust differential rail-to-rail delay cell. The delay cell is fabricated in a 3.3 V 0.35 μm CMOS process. The delay cell shows a wide-range operation and low power supply sensitivity. The delay range is 0.31 ps to 21.8 ns. For 0.5 ns delay, when the clock period is 500 MHz, the power supply sensitivity is 0.033 ps/mV. The delay cell is used in a DLL for clock generation of a four times interleaved 2 Gb/s decision feedback equalizer.

Place, publisher, year, edition, pages
Piscataway: IEEE, Inc., 2004
Keyword
Clocks, Decision feedback equalizers, Delay lines, Diodes, Jitter, MOSFETs, Power supplies, Resistors, Robustness, Signal generators
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-22505 (URN)10.1109/SOCC.2004.1362378 (DOI)1756 (Local ID)0-7803-8445-8 (ISBN)1756 (Archive number)1756 (OAI)
Conference
IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA.
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-01-25

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