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A digital circuit with relaxed clocking
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
2004 (English)In: Proc. Swedish System-on-Chip Conf., SSoCC'04, 2004Conference paper, Published paper (Other academic)
Abstract [en]

A clock with adjustable rise and fall time is used in conjunction with a D flip-flop that operates well with this clock. Its intended use is to relax the design of the clock network in digital circuits and to alleviate the problems with simultaneous switching noise in mixed-signal circuits. A test chip has been designed in a 0.35 μm CMOS process. The chip consists of a clock driver with adjustable rise and fall times, and an FIR filter that uses the special D flip-flop in the registers. According to measurements, the digital circuit works well when the rise and fall times of the clock is varied from 0.5 ns to 10 ns. This makes the propagation delay in the critical path to vary between 13.0 ns and 13.7 ns, and the energy dissipation to vary between 1.5 pJ and 1.7 pJ, for an input signal with a transition activity of 0.4.

Place, publisher, year, edition, pages
2004.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-22876Local ID: 2217OAI: oai:DiVA.org:liu-22876DiVA: diva2:243189
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-14

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Backenius, ErikVesterbacka, Mark

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