Non-Redundant Coding for Deep Sub-Micron Address Buses
2004 (English)In: IEEE International Workshop on System on Chip for Real-Time Applications,2004, Los Alamitos, California, USA: IEEE Computer Societiy , 2004, 275- p.Conference paper (Refereed)
A coding technique for deep sub-micron address buses with inter-wire capacitances dominating the wire-to-ground capacitances is presented. This code is similar to Gray codes, in the sense that it defines an ordering of the binary space, such that adjacent codewords dissipate little energy when sent consecutively. The ordering is shown to be close to optimal, as to the energy dissipation, when sending the whole sequence in order. A circuit diagram realizing the coder is presented, using only n-1 two-input gates, where n is the bus width. Simulations show an improvement in energy dissipation of more than 50% over an uncoded bus in several cases, depending on the data being coded.
Place, publisher, year, edition, pages
Los Alamitos, California, USA: IEEE Computer Societiy , 2004. 275- p.
Low-power VLSI, coding for low power
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-22896Local ID: 2247OAI: oai:DiVA.org:liu-22896DiVA: diva2:243209