A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances
2004 (English)In: IEEE International Workshop on System on Chip for Real-Time Applications,2004, Los Alamitos, California, USA: IEEE Computer Society , 2004, 257- p.Conference paper (Refereed)
In this paper we present a simplified model of parallel, on-chip buses, motivated by the movement toward CMOS technologies where the ratio between inter-wire capacitance and wire-to-ground capacitance is very large. We also introduce a ternary bus state representation, suitable for the bus model. Using this representation we propose a coding scheme without memory which reduces energy dissipation in the bus model by approximately 20-30% compared to an uncoded system. At the same time the proposed coding scheme is easy to realize, in terms of standard cells needed, compared to several previously proposed solutions.
Place, publisher, year, edition, pages
Los Alamitos, California, USA: IEEE Computer Society , 2004. 257- p.
Low-power VLSI, coding for low power
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-22901Local ID: 2252OAI: oai:DiVA.org:liu-22901DiVA: diva2:243214