Deep Sub-Micron Bus Invert Coding
2004 (English)In: Proceedings of the 6th Nordic Signal Processing Symposium, 2004. NORSIG 2004., Helsinki: University of Technology , 2004, 133-136 p.Conference paper (Refereed)
In this paper we present a simplified model for deep sub-micron, on-chip, parallel data buses. Using this model a coding technique similar to Bus Invert Coding is presented, but with a better performance in the proposed model. The coding technique can be realized using low-complexity encoding and decoding circuitry, and with a complexity that scales linearly with the bus width. Simulation results show that the energy dissipation decreases with approximately 20% for buses with up to 16 wires.
Place, publisher, year, edition, pages
Helsinki: University of Technology , 2004. 133-136 p.
coding for low power, low-power vlsi
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-22906Local ID: 2259ISBN: 951-22-7065-XOAI: oai:DiVA.org:liu-22906DiVA: diva2:243219
The 6th Nordic Signal Processing Symposium, 2004. NORSIG 2004, June 9 - 11, 2004, Meripuisto, Espoo, Finland