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An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
IDA Linköpings Universitet.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2004 (English)In: 2004 IEEE Asian Test Symposium ATS 2004,2004, Kenting, Taiwan: IEEE Computer Society Press , 2004, 254- p.Conference paper, Published paper (Refereed)
Abstract [en]

The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE's (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.

Place, publisher, year, edition, pages
Kenting, Taiwan: IEEE Computer Society Press , 2004. 254- p.
Keyword [en]
testing, fault coverage, defect probabilities, embedded systems
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23194Local ID: 2604OAI: oai:DiVA.org:liu-23194DiVA: diva2:243508
Available from: 2009-10-07 Created: 2009-10-07

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http://www.ida.liu.se/labs/eslab/publications/pap/db/ats04_stina.pdf

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Larsson, Erik

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CiteExportLink to record
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  • apa
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