Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems
2004 (English)In: International Conference on Computer Aided Design ICCAD 2004,2004, San Jose, USA: IEEE Computer Society Press , 2004, 362- p.Conference paper (Refereed)
In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption. The voltage scaling technique achieves energy efficiency by simultaneously scaling the supply and body bias voltages in the case of processors and buses with repeaters, while energy efficiency on fat wires is achieved through dynamic voltage swing scaling. We also introduce a set of accurate communication models for the energy estimation of voltage scalable embedded systems. In particular, we demonstrate that voltage scaling of bus repeaters and dynamic adaption of the voltage swing on fat wires can significantly influence the system's energy consumption. Experimental results, conducted on numerous generated benchmarks and a real-life example, demonstrate that substantial energy savings can be achieved with the proposed techniques.
Place, publisher, year, edition, pages
San Jose, USA: IEEE Computer Society Press , 2004. 362- p.
low power, voltage scaling, body bias, scheduling
IdentifiersURN: urn:nbn:se:liu:diva-23198DOI: 10.1109/ICCAD.2004.1382602Local ID: 2609ISBN: 0-7803-8702-3OAI: oai:DiVA.org:liu-23198DiVA: diva2:243512
International Conference on Computer Aided Design ICCAD 2004