A Formal Verification Methodology for IP-based Designs
2004 (English)In: EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools,2004, Rennes, France: IEEE Computer Society Press , 2004, 372- p.Conference paper (Refereed)
This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design, using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already verified by their designers and which are considered correct under the assumption that the environment satisfies certain properties assumed by the component. What remains to be verified is the glue logic inserted between the components. Each such glue logic is verified one at a time using model checking techniques. Experiments, performed on a real-life example (mobile telephone), demonstrating the efficiency and intuitivity of the methodology, are moreover thoroughly presented. Three different properties have been verified on one part of the system.
Place, publisher, year, edition, pages
Rennes, France: IEEE Computer Society Press , 2004. 372- p.
formal verification, component-based design, glue logic, model checking
IdentifiersURN: urn:nbn:se:liu:diva-23200DOI: 10.1109/DSD.2004.1333299Local ID: 2611ISBN: 0-7695-2203-3OAI: oai:DiVA.org:liu-23200DiVA: diva2:243514
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, DSD 2004