A Technique for Optimization of System-on-Chip Test Data Transportation
2004 (English)In: 9th IEEE European Test Symposium,2004, 2004, 179-180 p.Conference paper (Refereed)
We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.
Place, publisher, year, edition, pages
2004. 179-180 p.
system-on-chip, data transportation, test control logic
IdentifiersURN: urn:nbn:se:liu:diva-23206Local ID: 2617OAI: oai:DiVA.org:liu-23206DiVA: diva2:243520