Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
2005 (English)In: Design Automation and Test in Europe Conference DATE 2005,2005, Munich, Germany: IEEE Computer Society Press , 2005, 864- p.Conference paper (Refereed)
In this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2005. 864- p.
fault-tolerance, time-triggered, embedded systems, re-execution, replication, scheduling, mapping
IdentifiersURN: urn:nbn:se:liu:diva-23255DOI: 10.1109/DATE.2005.116Local ID: 2674ISBN: 0-7695-2288-2OAI: oai:DiVA.org:liu-23255DiVA: diva2:243569
Design Automation and Test in Europe Conference DATE 2005