A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
2004 (English)In: The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004,2004, 2004, 413-415 p.Conference paper (Refereed)
This paper describes a built-in self-test hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It considers both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.
Place, publisher, year, edition, pages
2004. 413-415 p.
BIST, design for testability, wiring overhead, testing
IdentifiersURN: urn:nbn:se:liu:diva-23293DOI: 10.1109/DELTA.2004.10073Local ID: 2719ISBN: 0-7695-2081-2OAI: oai:DiVA.org:liu-23293DiVA: diva2:243607
The IEEE International Workshop on Electronic Design, Test and Applications DELTA 2004