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Optimal System-on-Chip Test Scheduling
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Computer Design and Test Lab. Nara Inst. of Science and Technology.
2003 (English)In: 12th IEEE Asian Test Symposium ATS03,2003, Xian, China: IEEE Computer Society Press , 2003, p. 306-Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.

Place, publisher, year, edition, pages
Xian, China: IEEE Computer Society Press , 2003. p. 306-
Keywords [en]
test scheduling, test access mechanisms, TAM, test conflicts, test wrappers, TAM routing
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:liu:diva-23320Local ID: 2750OAI: oai:DiVA.org:liu-23320DiVA, id: diva2:243634
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2018-01-13

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http://www.ida.liu.se/labs/eslab/publications/pap/db/ats03_erila.pdf

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Larsson, Erik

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  • nn-NB
  • sv-SE
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Output format
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