Iterative Schedule Optimisation for Voltage scalable Distributed Embedded Systems
2004 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 3, no 1, 182-217 p.Article in journal (Refereed) Published
We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs).To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.
Place, publisher, year, edition, pages
2004. Vol. 3, no 1, 182-217 p.
dynamic voltage scaling, DVS, supply voltage, co-synthesis, energy reduction
IdentifiersURN: urn:nbn:se:liu:diva-23322DOI: 10.1145/972627.972636Local ID: 2752OAI: oai:DiVA.org:liu-23322DiVA: diva2:243636