Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003 (English)In: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03,2003, Cambridge, MA, USA: IEEE Computer Society Press , 2003, 385- p.Conference paper (Refereed)
Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs.
Place, publisher, year, edition, pages
Cambridge, MA, USA: IEEE Computer Society Press , 2003. 385- p.
test access mechanisms, TAM, system-on-chip, SOC, data transportation, constraint logic programming, test scheduling
National CategoryComputer Science
IdentifiersURN: urn:nbn:se:liu:diva-23326Local ID: 2756OAI: oai:DiVA.org:liu-23326DiVA: diva2:243640