Test Resource Partitioning and Optimization for SOC Designs
2003 (English)In: 2003 IEEE VLSI Test Symposium VTS03,2003, Napa Valley, USA: IEEE Computer Society Press , 2003, 319- p.Conference paper (Refereed)
We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.
Place, publisher, year, edition, pages
Napa Valley, USA: IEEE Computer Society Press , 2003. 319- p.
core-based design, resource floor-planning, test access mechanism, TAM, test scheduling, TAM routing
IdentifiersURN: urn:nbn:se:liu:diva-23335Local ID: 2766OAI: oai:DiVA.org:liu-23335DiVA: diva2:243649