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Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems
Dept. of Electronics and Computer Science University of Southampton.
Dept. of Electronics and Computer Science University of Southampton.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2003 (English)In: Design Automation and Test in Europe DATE 2003 Conference,2003, Munich, Germany: IEEE Computer Society Press , 2003, 90- p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.

Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2003. 90- p.
Keyword [en]
dynamic voltage scaling, DVS, conditional task graphs, genetic algorithm, energy saving, embedded systems
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23338Local ID: 2770OAI: oai:DiVA.org:liu-23338DiVA: diva2:243652
Available from: 2009-10-07 Created: 2009-10-07

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http://www.ida.liu.se/labs/eslab/publications/pap/db/date03_wu.pdf

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Eles, Petru Ion

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