An Integrated Framework for the Design and Optimization of SOC Test Solutions
2002 (English)In: SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. / [ed] Krishnendu Chakrabarty, Boston, USA: Kluwer Academic Publishers , 2002, 21-36 p.Chapter in book (Other academic)
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.
Place, publisher, year, edition, pages
Boston, USA: Kluwer Academic Publishers , 2002. 21-36 p.
, Frontiers in Electronic Testing, 21
SOC, system-on-chip, test power consumption, test optimization
IdentifiersURN: urn:nbn:se:liu:diva-23341Local ID: 2774ISBN: 1-4020-7205-8ISBN: 978-1-4020-7205-5OAI: oai:DiVA.org:liu-23341DiVA: diva2:243655