High-Level and Hierarchical Test Sequence Generation
2002 (English)In: IEEE International Workshop on High Level Design Validation and Test,2002, Cannes, France: IEEE Computer Society Press , 2002, 169- p.Conference paper (Refereed)
Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions.
The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at the gate-level, with comparable or even higher fault coverage. This paper first analyses several high-level fault models in order to select the most suitable one for estimating the testability of circuits by reasoning on their behavioral descriptions and for guiding the test generation process at the
behavioral level. We assess then the effectiveness of high-level test generation with a simple ATPG algorithm, and present a novel
high-level hierarchical test generation approach to improve the results obtained by a pure high-level test generator.
Place, publisher, year, edition, pages
Cannes, France: IEEE Computer Society Press , 2002. 169- p.
gate-level test generation, high-level test generation, high-level fault models, ATPG algorithm, hierarchical test generation, testing
IdentifiersURN: urn:nbn:se:liu:diva-23344Local ID: 2779OAI: oai:DiVA.org:liu-23344DiVA: diva2:243658