Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems
2003 (English)In: IEE journal on computers and digital techniques / Institution of electrical engineers, ISSN 0140-1335, Vol. 150, no 5, 303-312 p.Article in journal (Refereed) Published
We present an approach to schedulability analysis for the synthesis of multicluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.
Place, publisher, year, edition, pages
2003. Vol. 150, no 5, 303-312 p.
schedulability analysis, multi-cluster distributed embedded systems, time-triggered, event-triggered, routing inter-cluster traffic, bus access optimization
IdentifiersURN: urn:nbn:se:liu:diva-23346Local ID: 2781OAI: oai:DiVA.org:liu-23346DiVA: diva2:243660