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Integrated Test Scheduling, Test Parallelization and TAM Design
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Embedded Systems Lab. Linköpings Universitet.
Computer Design and Test Lab. Nara Inst. of Science and Technology.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2002 (English)In: IEEE Asian Test Symposium ATS02,2002, Tamuning, Guam, USA: IEEE Computer Society Press , 2002, 397- p.Conference paper, Published paper (Refereed)
Abstract [en]

We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.

Place, publisher, year, edition, pages
Tamuning, Guam, USA: IEEE Computer Society Press , 2002. 397- p.
Keyword [en]
test access mechanism, TAM, TAM routing, test scheduling, scan chain partitioning, test conflicts, power constraints
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23348Local ID: 2783OAI: oai:DiVA.org:liu-23348DiVA: diva2:243662
Available from: 2009-10-07 Created: 2009-10-07

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http://www.ida.liu.se/labs/eslab/publications/pap/db/ats02.pdf

Authority records BETA

Larsson, ErikPeng, Zebo

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Output format
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