An Approach to Reducing Verification Complexity of Real-Time Embedded Systems
2002 (English)In: 14th Euromicro Conference on Real-Time Systems ECRTS 2002, Work-in-Progress Session,2002, 2002, 45-48 p.Conference paper (Refereed)
We present an approach to the formal verification of real-time embedded systems by using model checking. We address the verification of systems modeled in a timed Petri net representation and introduce a technique for reducing verification complexity. We translate the Petri net based model into timed automata and make use of availablemodel checking tools to prove the correctness of the system with respect to design properties expressed in the temporal logics CTL and TCTL. Experimental results demonstrate considerable improvements in verification efficiency when the degree of parallelism of the system is considered.
Place, publisher, year, edition, pages
2002. 45-48 p.
real-time embedded systems, model checking, petri nets, timed automata, temporal logics
IdentifiersURN: urn:nbn:se:liu:diva-23352Local ID: 2787OAI: oai:DiVA.org:liu-23352DiVA: diva2:243666