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Power Constrained Preemptive TAM Scheduling
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Computer Design and Test Lab. Nara Inst. of Science and Technology.
2002 (English)In: 7th IEEE European Test Workshop,2002, Corfu, Greece: IEEE Computer Society Press , 2002, 119- p.Conference paper (Refereed)
Abstract [en]

We integrate scan-chain partitioning and preemptive test access mechanism (TAM) scheduling for core-based systems under power constraint. We also outline a flexible power conscious test wrapper to increase the flexibility in the scheduling process by (1) allowing several different bandwidths at cores and (2) controlling the cores test power consumption, which makes it possible to increase the test clock. We model the scheduling problem as a Bin-packing problem and we discuss the transformations: (1) TAM-time and (2) power-time and the possibilities to achieve an optimal solution and the limitations. We have implemented our proposed preemptive TAM scheduling algorithm and through experiments we demonstrate its efficiency.

Place, publisher, year, edition, pages
Corfu, Greece: IEEE Computer Society Press , 2002. 119- p.
Keyword [en]
scan-chain partitioning, core-based systems, power constraint, test access mechanism, TAM, preemptive TAM scheduling
National Category
Computer Science
URN: urn:nbn:se:liu:diva-23353Local ID: 2788OAI: diva2:243667
Available from: 2009-10-07 Created: 2009-10-07

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Larsson, Erik
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The Institute of TechnologyESLAB - Embedded Systems Laboratory
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