liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2002 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 18, no 4-5, 385-400 p.Article in journal (Refereed) Published
Abstract [en]

We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.

Place, publisher, year, edition, pages
2002. Vol. 18, no 4-5, 385-400 p.
Keyword [en]
SOC, test access mechanism, power consuption, test resource placement, test scheduling
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23363Local ID: 2799OAI: oai:DiVA.org:liu-23363DiVA: diva2:243677
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2017-12-13

Open Access in DiVA

No full text

Other links

http://www.ida.liu.se/labs/eslab/publications/pap/db/jetta02.pdf

Authority records BETA

Larsson, ErikPeng, Zebo

Search in DiVA

By author/editor
Larsson, ErikPeng, Zebo
By organisation
The Institute of TechnologyESLAB - Embedded Systems Laboratory
In the same journal
Journal of electronic testing
Computer Science

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 114 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf