The Design and Optimization of SOC Test Solutions
2001 (English)In: ICCAD-2001,2001, San Jose, California: IEEE Computer Society Press , 2001, 523- p.Conference paper (Refereed)
We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.
Place, publisher, year, edition, pages
San Jose, California: IEEE Computer Society Press , 2001. 523- p.
system-on-chip, testing, test conflicts, optimized design, embedded systems
IdentifiersURN: urn:nbn:se:liu:diva-23370Local ID: 2807OAI: oai:DiVA.org:liu-23370DiVA: diva2:243684