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Fast Test Cost Calculation for Hybrid BIST in Digital Systems
Dept. Computer Engineering Tallinn University of Technology.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Dept. Computer Engineering Tallinn University of Technology.
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2001 (English)In: Euromicro Symposium on Digital Systems Design,2001, Warsaw, Poland: IEEE Computer Society Press , 2001, 318- p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform core test with minimum cost of both, time and memory, and without losing in test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, in this paper a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.

Place, publisher, year, edition, pages
Warsaw, Poland: IEEE Computer Society Press , 2001. 318- p.
Keyword [en]
hybrid BIST, testing systems-on-chip, pseudorandom test patterns, deterministic test patterns, ATPG
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23374Local ID: 2811OAI: oai:DiVA.org:liu-23374DiVA: diva2:243688
Available from: 2009-10-07 Created: 2009-10-07

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http://www.ida.liu.se/labs/eslab/publications/pap/db/EM01-GERJE.pdf

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Jervan, GertPeng, Zebo

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Output format
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