liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Improving the Efficiency of Timing Simulation of Digital Circuits
Dept. Computer Engineering Tallinn University of Technology.
Dept. Computer Engineering Tallinn University of Technology.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2001 (English)In: Design, Automation and Test in Europe DATE Conference,2001, Munich, Germany: IEEE Computer Society Press , 2001, 460- p.Conference paper, Published paper (Refereed)
Abstract [en]

Meeting timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, a new approach and the implementation of several algorithms to speed up gate-level timing simulation are proposed where, instead of gate delays, path delays for tree-like subcircuits (macros) are used. Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit but only for outputs of macros. The macros are represented by structurally synthesized binary decision diagrams (SSBDD) which enable a fast computation of delays for macros. The new approach to speed up the timing simulation is supported by encouraging experimental results.

Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2001. 460- p.
Keyword [en]
highly integrated circuits, CAD tools, gate-level timing simulation, structurally synthesized binary decision diagrams, SSBDD
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23381Local ID: 2821OAI: oai:DiVA.org:liu-23381DiVA: diva2:243695
Available from: 2009-10-07 Created: 2009-10-07

Open Access in DiVA

No full text

Other links

http://www.ida.liu.se/labs/eslab/publications/pap/db/DATE_01_jutman.pdf

Authority records BETA

Peng, Zebo

Search in DiVA

By author/editor
Peng, Zebo
By organisation
The Institute of TechnologyESLAB - Embedded Systems Laboratory
Computer Science

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 55 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf