Improving the Efficiency of Timing Simulation of Digital Circuits
2001 (English)In: Design, Automation and Test in Europe DATE Conference,2001, Munich, Germany: IEEE Computer Society Press , 2001, 460- p.Conference paper (Refereed)
Meeting timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, a new approach and the implementation of several algorithms to speed up gate-level timing simulation are proposed where, instead of gate delays, path delays for tree-like subcircuits (macros) are used. Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit but only for outputs of macros. The macros are represented by structurally synthesized binary decision diagrams (SSBDD) which enable a fast computation of delays for macros. The new approach to speed up the timing simulation is supported by encouraging experimental results.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2001. 460- p.
highly integrated circuits, CAD tools, gate-level timing simulation, structurally synthesized binary decision diagrams, SSBDD
IdentifiersURN: urn:nbn:se:liu:diva-23381Local ID: 2821OAI: oai:DiVA.org:liu-23381DiVA: diva2:243695