An Integrated System-On-Chip Test Framework
2001 (English)In: Design, Automation and Test in Europe DATE Conference,2001, Munich, Germany: IEEE Computer Society Press , 2001, 138-144 p.Conference paper (Refereed)
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.
Place, publisher, year, edition, pages
Munich, Germany: IEEE Computer Society Press , 2001. 138-144 p.
testing, system-on-chip, test access mechanism selection, test parallelization, test resource placement, power consumption, embedded systems
National CategoryComputer Science
IdentifiersURN: urn:nbn:se:liu:diva-23382DOI: 10.1109/DATE.2001.915014Local ID: 2822ISBN: 0-7695-0993-2OAI: oai:DiVA.org:liu-23382DiVA: diva2:243696
Design, Automation and Test in Europe, 13-16 March 2001, Munich, Germany