Verification of Embedded Systems using a Petri Net based Representation
2000 (English)In: 13th International Symposium on System Synthesis ISSS 2000,2000, Madrid, Spain: IEEE Computer Society Press , 2000, 149-155 p.Conference paper (Refereed)
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness. New verification methods that overcome the limitations of traditional techniques and, at the same time, are suitable for hardware/software systems are needed. In this work we formally define the semantics of PRES+, a Petri net based computational model aimed to represent embedded systems. We introduce an approach to formal verification of such systems: we make use of model checking to prove the correctness of embedded systems by determining the truth of CTL and TCTL formulas that specify required properties with respect to a PRES+ model. An ATM server illustrates the feasibility of our approach on practical applications.
Place, publisher, year, edition, pages
Madrid, Spain: IEEE Computer Society Press , 2000. 149-155 p.
embedded systems, formal verification, PRES+, petri nets, hardware software co-design
IdentifiersURN: urn:nbn:se:liu:diva-23385DOI: 10.1109/ISSS.2000.874042Local ID: 2825ISBN: 0-7695-0765-4OAI: oai:DiVA.org:liu-23385DiVA: diva2:243699
13th International Symposium on System Synthesis, 20-22 September, Madrid, Spain