Definitions of Equivalence for Transformational Synthesis of Embedded Systems
2000 (English)In: 6th International Conference on Engineering of Complex Computer Systems ICECCS 2000,2000, Tokyo, Japan: IEEE Computer Society Press , 2000, 134-142 p.Conference paper (Refereed)
Design of embedded systems is a complex task that requires design cycles founded upon formal notation, so that the synthesis from specification to implementation can be carried out systematically. In this paper we present a computational model for embedded systems based on Petri nets called PRES+. It includes an explicit notion of time and allows a concise formulation of models. Tokens, in our notation, hold information and transitionsÑwhen firedÑperform transformation of data. Based on this model we define several notions of equivalence (reachable, behavioral, time, and total), which provide the framework for transformational synthesis of embedded systems. Different representations of an Ethernet network coprocessor are studied in order to illustrate the applicability of PRES+ and the definitions of equivalence on practical systems.
Place, publisher, year, edition, pages
Tokyo, Japan: IEEE Computer Society Press , 2000. 134-142 p.
formal verification, embedded system design, petri nets, PRES+, modeling
IdentifiersURN: urn:nbn:se:liu:diva-23386DOI: 10.1109/ICECCS.2000.873937Local ID: 2826ISBN: 0-7695-0583-XOAI: oai:DiVA.org:liu-23386DiVA: diva2:243700
Sixth IEEE International Conference on Engineering of Complex Computer Systems, 11-14 September 2000, Tokyo, Japan