System-on-Chip Test Parallelization Under Power Constraints
2001 (English)Other (Other (popular science, discussion, etc.))
This paper deals
with test parallelization (scan-chain sub-division) which is used
as a technique to reduce test application time for systems-on-chip.
An approach for test parallelization taking into account test
conflicts and test power limitations is described. The main
features of the proposed approach are the combination of test
parallelization with test scheduling as well as the development of
an extremely fast algorithm which can be used repeatedly in the
design space exploration process. The efficiency and usefulness of
our approach have been demonstrated with an industrial
Place, publisher, year, edition, pages
Stockholm, Sweden: European Test Workshop , 2001.
test parallelization, scan-chain, test conflicts
IdentifiersURN: urn:nbn:se:liu:diva-23400Local ID: 2842OAI: oai:DiVA.org:liu-23400DiVA: diva2:243714