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System-on-Chip Test Parallelization Under Power Constraints
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2001 (English)Other (Other (popular science, discussion, etc.))
Abstract [en]

This paper deals with test parallelization (scan-chain sub-division) which is used as a technique to reduce test application time for systems-on-chip. An approach for test parallelization taking into account test conflicts and test power limitations is described. The main features of the proposed approach are the combination of test parallelization with test scheduling as well as the development of an extremely fast algorithm which can be used repeatedly in the design space exploration process. The efficiency and usefulness of our approach have been demonstrated with an industrial design.

Place, publisher, year, pages
Stockholm, Sweden: European Test Workshop , 2001.
Keyword [en]
test parallelization, scan-chain, test conflicts
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23400Local ID: 2842OAI: oai:DiVA.org:liu-23400DiVA: diva2:243714
Available from: 2009-10-07 Created: 2009-10-07

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http://www.ida.liu.se/labs/eslab/publications/pap/db/ETW01.pdf

Authority records BETA

Larsson, ErikPeng, Zebo

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