BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints
2001 (English)Other (Other (popular science, discussion, etc.))
This paper describes an approach to optimize BIST resource usage for system on chip under testing time constraints.
A symbolic testability analysis technique is used to analyze testability of the design for pseudorandom BIST. The testability analysis results are used to guide high-level synthesis of system on chip blocks with BIST mechanisms. Finally, BIST resources are optimized to comply with test time constraints. Key words: BIST, testing time, symbolic testability analysis, and high-level BIST synthesis.
Place, publisher, year, edition, pages
Santa Barbara, USA: International Test Synthesis Workshop , 2001.
testing, BIST, wiring-aware
IdentifiersURN: urn:nbn:se:liu:diva-23401Local ID: 2843OAI: oai:DiVA.org:liu-23401DiVA: diva2:243715