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BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2001 (English)Other (Other (popular science, discussion, etc.))
Abstract [en]

This paper describes an approach to optimize BIST resource usage for system on chip under testing time constraints. A symbolic testability analysis technique is used to analyze testability of the design for pseudorandom BIST. The testability analysis results are used to guide high-level synthesis of system on chip blocks with BIST mechanisms. Finally, BIST resources are optimized to comply with test time constraints. Key words: BIST, testing time, symbolic testability analysis, and high-level BIST synthesis.

Place, publisher, year, pages
Santa Barbara, USA: International Test Synthesis Workshop , 2001.
Keyword [en]
testing, BIST, wiring-aware
National Category
Computer Science
Identifiers
URN: urn:nbn:se:liu:diva-23401Local ID: 2843OAI: oai:DiVA.org:liu-23401DiVA: diva2:243715
Available from: 2009-10-07 Created: 2009-10-07

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Mohamed, AbdilPeng, ZeboEles, Petru Ion

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Mohamed, AbdilPeng, ZeboEles, Petru Ion
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