Power estimation for bit-serial constant coefficient multipliers
2004 (English)In: Swedish System-on-Chip Conference 2004,2004, 2004Conference paper (Other academic)
In this work a model for estimation of the power consumption in bit-serial, constant coefficient multipliers is presented. The multipliers are implemented using shift-add operations. Model parameters for the required components, i.e., flip-flops and full-adders, are derived. The power for a multiplier is obtained by summing the power for all components included in the corresponding network of shifts and adders.
Place, publisher, year, edition, pages
Power estimation multipliers
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-23639Local ID: 3132OAI: oai:DiVA.org:liu-23639DiVA: diva2:243954
The Swedish System-on-Chip Conference 2004, April 13-14, Båstad, Sweden