Design of a comparator in CMOS SOI
2004 (English)In: Proc. 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, 229-232 p.Conference paper (Refereed)
This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 μm partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz.
Place, publisher, year, edition, pages
2004. 229-232 p.
CMOS integrated circuits, analog-digital conversion, comparators (circuits), integrated circuit design, silicon-on-insulator
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-23649Local ID: 3143ISBN: 0-7695-2182-7OAI: oai:DiVA.org:liu-23649DiVA: diva2:243964