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Implementation of bit-level pipelined digit-serial multipliers
Mälardalen University .
Mälardalen University Department of Electronics, Västerås, Sweden.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.ORCID iD: 0000-0003-3470-3911
2004 (English)In: Proceedings of the 6th Nordic Signal Processing Symposium - NORSIG 2004, June 9-11, 2004, Espoo, Finland, 2004, 125-128 p.Conference paper (Refereed)
Abstract [en]

In this paper, a digit-serial multiplier based on shift-accumulation (DSAAM) [1] is compared to a digit-serial/parallel multiplier (S|/Ppipe) [2]. Both the studied multipliers can be pipelined to an arbitrary degree and are, therefore, well suited for high-throughput implementation. In our study bit-level pipelining was considered. Neither of the multipliers have been implemented in a deep-submicron technology previously, which motivates our study. The multipliers were implemented using a 0.18 μm standard cell technology, and the area, throughput and current consumptionwas analyzed. It was concluded that the DSAAM can be implemented with a lower latency than the (S/Ppipe, leading to a higher throughput and lower area and current consumption. Onaverage the area and current consumption of the DSAAM is 50% and 52% lower than for the S/Ppipe, respectively. Furthermore, the throughput of the DSAAM is 37% higher.

Place, publisher, year, edition, pages
2004. 125-128 p.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-23653Local ID: 3147ISBN: 951-22-7065-XOAI: diva2:243968
The 6th Nordic Signal Processing Symposium - NORSIG 2004, June 9-11, 2004, Espoo, Finland
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2015-03-11Bibliographically approved

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