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Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.ORCID iD: 0000-0003-3470-3911
Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
2004 (English)In: Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference, 2004. MELECON 2004, Volume 1, IEEE , 2004, 197-200 p.Conference paper, Published paper (Other academic)
Abstract [en]

In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.

Place, publisher, year, edition, pages
IEEE , 2004. 197-200 p.
Keyword [en]
Algorithm multiplier serial arithmetic
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-23663DOI: 10.1109/MELCON.2004.1346807Local ID: 3157ISBN: 0-7803-8271-4 (print)OAI: oai:DiVA.org:liu-23663DiVA: diva2:243978
Conference
12th IEEE Mediterranean Electrotechnical Conference, 2004. MELECON 2004, May 12-15, Dubrovnik, Croatia
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2015-03-11Bibliographically approved

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Johansson, KennyGustafsson, OscarWanhammar, Lars

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Citation style
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Language
  • de-DE
  • en-GB
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  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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Output format
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