Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic
2004 (English)In: Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference, 2004. MELECON 2004, Volume 1, IEEE , 2004, 197-200 p.Conference paper (Other academic)
In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.
Place, publisher, year, edition, pages
IEEE , 2004. 197-200 p.
Algorithm multiplier serial arithmetic
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-23663DOI: 10.1109/MELCON.2004.1346807Local ID: 3157ISBN: 0-7803-8271-4OAI: oai:DiVA.org:liu-23663DiVA: diva2:243978
12th IEEE Mediterranean Electrotechnical Conference, 2004. MELECON 2004, May 12-15, Dubrovnik, Croatia