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Low-complexity bit-serial constant-coefficient multipliers
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.ORCID iD: 0000-0003-3470-3911
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2004 (English)In: Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, Volume 3, IEEE , 2004, 649-652 p.Conference paper, Published paper (Other academic)
Abstract [en]

In this work we investigate the possibilities to minimize the complexity of bit-serial constant-coefficient multipliers. This is done in terms of number of required building blocks, which includes adders and flip-flops. The multipliers are described using a graph representation. We show that it is possible to find a minimum set of graphs that are required to get optimal results for the different multiplier types. The complexity cost for these multipliers are then investigated. Most results are compared to multipliers that adopt the commonly used canonic signed-digit representation.

Place, publisher, year, edition, pages
IEEE , 2004. 649-652 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-23666DOI: 10.1109/ISCAS.2004.1328830Local ID: 3161ISBN: 0-7803-8251-X (print)OAI: oai:DiVA.org:liu-23666DiVA: diva2:243981
Conference
The 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04, May 23-26, Vancouver, Canada
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2015-03-11Bibliographically approved

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Johansson, KennyGustafsson, OscarWanhammar, Lars

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Citation style
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  • de-DE
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  • nn-NB
  • sv-SE
  • Other locale
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