A high-speed low-latency digit-serial hybrid adder
2004 (English)In: IEEE Int. Symp. on Circuits and Systems, ISCAS'04, 2004, III-217-III-220 p.Conference paper (Refereed)
In this paper, we present a new digit-serial hybrid adder. The adder can be pipelined to the bit-level and is, therefore, well suited for high-speed applications. The main advantage of the proposed adder is that it can be implemented with few pipelining stages. We compare speed, area, and power consumption for the proposed adder with a digit-serial carry-look-ahead adder and a digit-serial Ladner-Fisher adder. The results show that the delay of the digit-serial hybrid adder is lower than the others studied in this paper for digit-sizes up to d=12. For these digit-sizes the digit-serial hybrid adder has on average 17% smaller critical path than the digit-serial carry-look-ahead adder and a 21% smaller critical path that the digit-serial Ladner-Fisher adder.
Place, publisher, year, edition, pages
2004. III-217-III-220 p.
adders, digital arithmetic, pipeline processing
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-23671DOI: 10.1109/ISCAS.2004.1328722Local ID: 3166ISBN: 0-7803-8251-XOAI: oai:DiVA.org:liu-23671DiVA: diva2:243986