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A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers
ISY .
Linköping University, Department of Electrical Engineering, Electronics System.
2004 (English)In: Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS'04, 2004, 425-428 p.Conference paper, Published paper (Refereed)
Abstract [en]

Fixed coefficient digit-serial/parallel multipliers are presented. The multipliers are based on unfolded bit-serial/parallel multipliers in combination with canonic signed-digit coding of the fixed coefficient. The unfolding yields long critical paths, which cannot be pipelined due to the feed back carry loops, and carry-look-ahead techniques cannot be applied efficiently since the propagating sum path will increase. By using canonic signed-digit code the multiplier gains higher throughput and lower latency since the critical path is reduced without pipelining. Hence, the throughput is increased with between 56 and 150 percent compared with two's complement coded coefficients, and for the digit-sizes {2,3,4} it has the same throughput as the corresponding digit-serial adder.

Place, publisher, year, edition, pages
2004. 425-428 p.
Keyword [en]
adders, circuit feedback, encoding, multiplying circuits, pipeline arithmetic
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-23673Local ID: 3168ISBN: 0-7803-8251-X (print)OAI: oai:DiVA.org:liu-23673DiVA: diva2:243988
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2009-10-14

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Vesterbacka, Mark

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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Language
  • de-DE
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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Output format
  • html
  • text
  • asciidoc
  • rtf