The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures dedicated for processing of packets and network protocols.
In the emerging research area of protocol processing, there exist many hardware platform proposals. Most of them aim for router applications, not so many for terminals. As a starting point for terminal research this thesis explores a number of different router design alternatives and some common computer architecture concepts. These concepts and architectures have been examined and evaluated to see if some ideas apply also to protocol processing in network terminals.
Requirements on protocol processors for terminals can be summarized as:
• Low silicon area
• Low power consumption
• Low processing latency
• High processing throughput
• Flexible implementation
Fulfilling these requirements while supporting offtoading of as much protocol processing as possible to the network interface is the key issue of this thesis. Off-loading means that the protocol processing can be executed in a special unit that does not need to execute the host applications as well. The protocol processor unit basically acts as a smart network interface card.
A novel terminal platform solution is proposed in this thesis. The dual processor platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, which operate in parallel, to accelerate the platform in a configurable way. These hardware blocks have been selected and specified to fulfill requirements set by a number of common network protocols. To find these requirements, the protocol processing procedure has been investigated and divided into processing tasks. These different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in the other part of the platform which is a general purpose micro controller.
The dedicated datapath, simplified control, and minimal usage of data buffers make the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled. Different implementation alternatives are provided in this thesis. Which one to select depends on what kind of terminal the platform is going to be used for. Further this thesis includes a discussion around how the ability to reassembly fragmented packets demands architectural modifications.
Linköping: Linköpings universitet , 2004. , 162 p.
2004-04-23, Sal Visionen, Linköpings Universitet, Linköping, 10:15 (Swedish)