A Hardware Architecture for a Multi Mode Block Interleaver
2004 (English)In: International Conference on Circuits and Systems for Communications, ICCSC,2004, 2004Conference paper (Refereed)
We are interested in developing a programmable baseband processor for software defined radio and are trying to find configurable hardware blocks that can be used in multiple radio standards, including for example wireless LAN and 3G standards. This paper suggests an architecture for a multi mode block interleaver that is suitable e.g. for the IEEE 802.11a and 802.11g standards. Our implementation is based on a special matrix memory to which data is written as rows but read out as columns. To enable a comparison, an interleaver for theWireless LAN standard 802.11a has been implemented both using our suggested architecture and using a traditional interleaver implementation based on a bit memory. Our implementation reaches a significantly higher performance and a lower power consumption with no extra area. The price to pay is a small loss of generality.
Place, publisher, year, edition, pages
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-24105Local ID: 3678OAI: oai:DiVA.org:liu-24105DiVA: diva2:244422