Development and performance evaluation of networks on chip
2005 (English)Doctoral thesis, monograph (Other academic)
Along with Moore's law there is a continuous development in architectures for electronic systems. Currently there is a trend towards integration of more and more processing elements, e.g. general-purpose processors and DSPs, onto a single chip. With the increasing complexity of such systems come difficulties in creating a proper communications infrastructure for the chip. When time-division buses and custom point to point communication are no longer sufficient, more elaborate networks are the obvious choice. By turning from the current path of buses and custom communication designs for the higher levels of interconnection on the chip, it is possible to reach high performance with lower design and verification costs.
This thesis presents a circuit-switched network for on-chip use that has been developed with signal processing tasks in mind. The network implementation is simple and thus area efficient while being able to operate at high speed. Circuit-switched technology has the advantage of allowing very simple network components while giving high performance for many applications in the telecom area where intra-system communication often can be scheduled tightly according to the performance requirements of the system.
Parts of the design flow CAD support have been implemented along with the network components. An extendable, event-driven simulator has been developed that allows for updates and elaboration of both network components and processing modules.
The simulator has been used as the basis to develop a general method for benchmarking of networks on chip, where the end result should be comparable across different platforms and implementations. The performance of complex systems such as networks is not easily expressed analytically. Thus, the simulator is of paramount importance in assessing the performance of the network in an application.
The network implementation and simulation environment have been used for analysis of some applications. Applications that have been more thoroughly investigated are a single chip Internet core router and the baseband part of a 3GWCDMA/FDD radio basestation. The core router showed a performance in excess of 14 Gbit/s per port at 16 ports with realistic traffic. The 3G basestation application showed the applicability of the network for systems with lower requirements on communication bandwidth where significant savings in design effort can be made through the simplicity of the network system.
Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2005. , 168 p.
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 932
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-24113Local ID: 3689ISBN: 91-85297-62-3OAI: oai:DiVA.org:liu-24113DiVA: diva2:244430
2005-04-15, Sal Visionen, Campus Valla, Linköping, 15:15 (Swedish)
Svensson, Lars, Dr