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Hardware for speech and audio coding
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2004 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

While the Micro Processors (MPUs) as a general purpose CPU are converging (into Intel Pentium), the DSP processors are diverging. In 1995, approximately 50% of the DSP processors on the market were general purpose processors, but last year only 15% were general purpose DSP processors on the market. The reason general purpose DSP processors fall short to the application specific DSP processors is that most users want to achieve highest performance under minimized power consumption and minimized silicon costs. Therefore, a DSP processor must be an Application Specific Instruction set Processor (ASIP) for a group of domain specific applications.

An essential feature of the ASIP is its functional acceleration on instruction level, which gives the specific instruction set architecture for a group of applications. Hardware acceleration for digital signal processing in DSP processors is essential to enhance the performance while keeping enough flexibility. In the last 20 years, researchers and DSP semiconductor companies have been working on different kinds of accelerations for digital signal processing. The trade-off between the performance and the flexibility is always an interesting question because all DSP algorithms are "application specific"; the acceleration for audio may not be suitable for the acceleration of baseband signal processing. Even within the same domain, for example speech CODEC (COder/DECoder), the acceleration for communication infrastructure is different from the acceleration for terminals.

Benchmarks are good parameters when evaluating a processor or a computing platform, but for domain specific algorithms, such as audio and speech CODEC, they are not enough. The solution here is to profile the algorithm and from the resulting statistics make the decisions. The statistics also suggest where to start optimizing the implementation of the algorithm. The statistics from the profi ling has been used to improve implementations of speech and audio coding algorithms, both in terms of the cycle cost and for memory efficiency, i.e. code and data memory.

In this thesis, we focus on designing memory efficient DSP processors based on instruction level acceleration methods and data type optimization techniques. Four major areas have been attacked in order to speed up execution and reduce memory The first one is instruction level acceleration, where consecutive instructions appear frequently and are merged together. By this merge the code memory size is reduced and execution becomes faster. Secondly, complex addressing schemes are solved by acceleration for address calculations, i.e. dedicated hardware are used for address calculations. The third area, data storage and precision, is speeded up by using a reduced floating point scheme. The number of bits is reduced compared to the normal IEEE 754 floating point standard. The result is a lower data memory requirement, yet enough precision for the application; an mp3 decoder. The fourth contribution is a compact way of storing data in a general CPU. By adding two custom instructions, one load and one store, the data memory efficiency can be improved without making the firmware complex. We have tried to make application specific instruction sets and processors and also tried to improve processors based on an available instruction set.

Experiences from this thesis can be used for DSP design for audio and speech applications. They can additionally be used as a reference to a general DSP processor design methodology.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet , 2004. , 48 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1093
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-24115Local ID: 3691ISBN: 91-7373-953-7 (print)OAI: oai:DiVA.org:liu-24115DiVA: diva2:244432
Presentation
2004-06-02, Alan Turing (Estraden), Linköpings universitet, Linköping, 13:15 (Swedish)
Opponent
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2013-11-26
List of papers
1. Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.729
Open this publication in new window or tab >>Instruction and Hardware Acceleration in G.723.1 (6.3/5.3) and G.729
2001 (English)In: Proceedings of the 1st IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), 2001, 34-39 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper makes accelerations on instruction level based on the three speech coding algorithms G.723.1, 6.3 kbit/s and 5.3 kbit/s and G.729 8 kbit/s with hardware implementation. All these three algorithms are proposed by the H.323 standard together with G.711 64 kbit/s and G.728 16 kbit/s. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions [I], [2]. Three hardware structures are proposed to increase the performance.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33605 (URN)19639 (Local ID)19639 (Archive number)19639 (OAI)
Conference
The 1st IEEE International Symposium on Signal Processing and Information Technology, December 28-30, 2001, Cairo, Egypt
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-26
2. Instruction and hardware acceleration for MP-MLQ in G.723.1
Open this publication in new window or tab >>Instruction and hardware acceleration for MP-MLQ in G.723.1
2002 (English)In: IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02)., 2002, 235-239 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes a significant improvement in complexity for the higher bit rate, 6.3 kbit/s, speech coding algorithm G.723.1. The solution is to reduce the number of multiplications of the most computing extensive part of the algorithm. This part stands for around 50% of the total complexity. This is done by identifying and excluding multiplication with zeros. G.723.1 is one of the proposed speech coders in the H.323 standard. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions. A hardware structure for an application specific instruction set processor (ASIP) is proposed to increase the performance.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-33543 (URN)10.1109/SIPS.2002.1049715 (DOI)19568 (Local ID)0-7803-7587-4 (ISBN)19568 (Archive number)19568 (OAI)
Conference
IEEE Workshop on Signal Processing Systems, 2002. (SIPS '02). San Diego, California, USA. October 16-18, 2002.
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-26
3. Reduced floating point for MPEG1/2 layer III decoding
Open this publication in new window or tab >>Reduced floating point for MPEG1/2 layer III decoding
2004 (English)In: IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004, V-209-12 vol.5- p.Conference paper, Published paper (Refereed)
Abstract [en]

A new approach to decode MPEG 1/2-layer III, mp3, is presented. Instead of converting the algorithm to fixed point, we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually, new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementations we can use this 16-bit floating point easily. In addition, this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model have been completed.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-24100 (URN)10.1109/ICASSP.2004.1327084 (DOI)3672 (Local ID)0-7803-8484-9 (ISBN)3672 (Archive number)3672 (OAI)
Conference
International Conference on Acoustics, Speech and Signal Processing (ICASSP'04). Montreal, Quebec, Canada. May 17-21 2004.
Available from: 2009-10-07 Created: 2009-10-07 Last updated: 2015-02-18
4. Bit memory instructions for a general CPU
Open this publication in new window or tab >>Bit memory instructions for a general CPU
2004 (English)In: 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, 2004.Proceedings., 2004, 215-218 p.Conference paper, Published paper (Refereed)
Abstract [en]

Embedded memories in an application specific integrated circuit (ASIC) consume most of the chip area. Data variables of different widths require more memory than needed because they are rounded up to nearest power of 2, i.e., 6 to 8 bits, 11 to 16 bits, and 25 to 32 bits. This can be avoided by adding two bit oriented load and store instructions. The memories can still be 8, 16 or 32 bits wide, but the loads and stores can have arbitrary variable sizes. The hardware changes within the processor are small and an extra hardware block between the processor and the memory is added.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-102009 (URN)10.1109/IWSOC.2004.1319881 (DOI)0-7695-2182-7 (ISBN)
Conference
The 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04). Banff, Alberta, Canada. July 19-21 2004.
Available from: 2013-11-26 Created: 2013-11-26 Last updated: 2013-11-26

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